AMD Achieves 2nm Milestone with EPYC 'Venice' on TSMC N2 Process

AMD has achieved a significant milestone with the successful 'bring up' of its first 2nm-class silicon, the Venice CCD, marking it as the first high-performance computing (HPC) product to utilize TSMC's advanced N2 process technology. This achievement underscores the strong collaboration between AMD and TSMC, with both companies emphasizing the benefits of their partnership in driving innovation and performance enhancements. The Venice processor, based on AMD's Zen 6 microarchitecture, is set to launch next year and aims to deliver notable improvements in speed and power efficiency. Dr. Lisa Su, AMD's CEO, highlighted the importance of this collaboration, while TSMC's leadership expressed pride in AMD being a lead customer for their N2 process. This development positions AMD favorably against competitors like Intel, which is targeting a later release for its Xeon processors. Overall, AMD's progress reflects its commitment to advancing semiconductor technology and U.S. manufacturing.